/*--------------------------------------------------------------------------
SS888X.H

Header file for Sinh Micro SS888X microcontroller.
--------------------------------------------------------------------------*/

#ifndef __REG_SS888X_H__
#define __REG_SS888X_H__

/*
 * BYTE Register
 */

/* MCU Core */
sfr SP          = 0x81;
sfr DPL         = 0x82; 
sfr DPH         = 0x83;
sfr DPSEL       = 0x92; 
sfr PSW         = 0xD0; 
sfr ACC         = 0xE0; 
sfr B           = 0xF0; 

/* Power */
sfr PCON        = 0x87; 
sfr PWRCON0     = 0xF8;
sfr PWRCON1     = 0xF9;
sfr PWRCON2     = 0xFB;
sfr PWRCON3     = 0xFC;
sfr PWRCON4     = 0xFE;
sfr PWRSTAT     = 0xFD;

/* Clock */
sfr CKCON       = 0x8E; 
sfr RCCON       = 0xA6;
sfr CLKCON0     = 0xB0;
sfr CLKCON1     = 0xB1;
sfr CLKCON2     = 0x92;
/* Reset */
sfr RESETS      = 0xA0;
sfr RESETS0     = 0xA0;

/* watchdog */
sfr WDTCON      = 0x86;

/* Charger */
sfr CHGCON0     = 0xB6;
sfr CHGCON1     = 0xB2;
sfr CHGCON2     = 0xB3;
sfr CHGCON3     = 0xB5;
sfr CHGCON4     = 0x9F;
sfr CHGCON5     = 0xB4;
sfr CHGSTAT     = 0xB7;
sfr BATSTAT     = 0xFF;

/* I/O port */
sfr P0DAT       = 0x80;
sfr P0          = 0x80; // Dummy name
sfr P0MOD       = 0x95;
sfr P0PU        = 0x96;
sfr P0PD        = 0x97;
sfr P1DAT       = 0x90;
sfr P1          = 0x90;
sfr P1MOD       = 0x91;
sfr P1OM        = 0x93;
sfr P1PUPD      = 0x94;
sfr P2DAT       = 0xD8;
sfr P2          = 0xD8;
sfr P2MOD       = 0xD9;
sfr PWKCTL      = 0xA7;
sfr IOSTPCON0   = 0xA7;
sfr PDRV0       = 0xAA;
sfr PDRV1       = 0xAF;
sfr MFP0        = 0xAB;
sfr MFP1        = 0xAC;
sfr MFP2        = 0xAD;
sfr MFP3        = 0xAE;


/* Interrupt */
sfr INTCON0     = 0xA8;
sfr INTCON1     = 0xB8;
sfr INTCON2     = 0xC0;
sfr INTEN0      = 0xA8;
sfr INTEN1      = 0xB8;
sfr INTEN2      = 0xC0;
sfr INTEN3      = 0xDF;
sfr EINTCON     = 0xA9;
sfr INTPRIO     = 0xB9;


/* Timer */
sfr TCON        = 0x88;
sfr TCON1       = 0xA1;
sfr TMOD        = 0x89;
sfr TL0         = 0x8A;
sfr TL1         = 0x8B;
sfr TH0         = 0x8C;
sfr TH1         = 0x8D;
sfr TPDL0       = 0xA2;
sfr TBLNCON0    = 0xA2; // TPDL0/TBLNCON0
sfr TPDH0       = 0xA3;
sfr TPDL1       = 0xA4;
sfr TBLNCON1    = 0xA4; // TPDL1/TBLNCON1
sfr TPDH1       = 0xA5;

sfr T2CON       = 0xC8;
sfr T2MOD       = 0xC1;
sfr T2STAT      = 0xC9;
sfr T2D0        = 0xC2;
sfr TL2         = 0xC2; // dummy name
sfr T2D1        = 0xC3;
sfr TRL2        = 0xC3; // dummy name
sfr T2D2        = 0xC4;
sfr TCC0L       = 0xC4; // dummy name
sfr T2D3        = 0xC5;
sfr TCC1L       = 0xC5; // dummy name
sfr T2D4        = 0xC6;
sfr TCC2L       = 0xC6; // dummy name
sfr T2D5        = 0xC7;
sfr TCC3L       = 0xC7; // dummy name
sfr T2D6        = 0xCA;
sfr TCC0H       = 0xCA; // dummy name
sfr TH2_0       = 0xCA; // dummy name
sfr T2D7        = 0xCB;
sfr TCC1H       = 0xCB; // dummy name
sfr TRH2_0      = 0xCB; // dummy name
sfr T2D8        = 0xCC;
sfr TCC2H       = 0xCC; // dummy name
sfr TH2_1       = 0xCC; // dummy name
sfr T2D9        = 0xCD;
sfr TCC3H       = 0xCD; // dummy name
sfr TRH2_1      = 0xCD; // dummy name

/* LCD */
sfr LCDCON      = 0xD7;

/* Serial */
sfr SCON        = 0x98;
sfr U0CON       = 0x98;
sfr SBUF        = 0x99;
sfr U0BUF       = 0x99;
sfr SBR         = 0x9A;
sfr U0BR        = 0x9A;

/* I2C0 */
sfr IICCON      = 0xD1;
sfr IIC0CON     = 0xD1;
sfr IICSTAT     = 0xD2;
sfr IIC0STAT    = 0xD2;
sfr IICADDR     = 0xD3;
sfr IIC0ADDR    = 0xD3;
sfr IICDAT      = 0xD4;
sfr IIC0DAT     = 0xD4;
sfr IICDIV      = 0xD5;
sfr IIC0DIV     = 0xD5;


/* ADC */
sfr ADCCON0     = 0xE6;
sfr ADCCON1     = 0xE7;
sfr ADCCON2     = 0xF5;
sfr ADCCON3     = 0xF7;
sfr ADCCON4     = 0xFA;

sfr ADCCHEN     = 0xE8;
sfr ADCDAT0L    = 0xE1;
sfr ADCDAT1L    = 0xE9;
sfr ADCDAT01H   = 0xEA;
sfr ADCDAT2L    = 0xEB;
sfr ADCDAT3L    = 0xEC;
sfr ADCDAT23H   = 0xED;
sfr ADCDAT4L    = 0xEE;
sfr ADCDAT5L    = 0xEF;
sfr ADCDAT45H   = 0xF1;
sfr ADCDAT6L    = 0xF2;
sfr ADCDAT7L    = 0xF3;
sfr ADCDAT67H   = 0xF4;

sfr DCMPCON0    = 0xBD;
sfr DCMPCON1    = 0xBE;
sfr DCMPNDATL   = 0xBF;

sfr NTC1CON     = 0xDA;

/* IFR */
sfr IFR_ADR = 0xDB;
sfr IFR_DAT = 0xDC;
/* CMP */
sfr CMPCON0     = 0xBA;
sfr CMPCON1     = 0xBB;
sfr CMPCON2     = 0xBC;

/* PFOU */
sfr PRCCON0     = 0xE2;
sfr PRCCON1     = 0xE3;
sfr PRCCON2     = 0xD6;
sfr PRCFREQL    = 0xE4;
sfr DLLCON0     = 0xE5;
sfr DLLCON1     = 0xCF;
sfr HPWMCON0    = 0x9B;
sfr HPWMDZT0    = 0x9C;
sfr HPWMDZT1    = 0x9D;

sfr EFRADR      = 0x84;
sfr EFRDAT      = 0x85;

sfr TICKCON     = 0x8F;

/*
 * BIT Register
 */

/*  PSW   */
sbit CY         = 0xD7; 
sbit AC         = 0xD6; 
sbit F0         = 0xD5; 
sbit RS1        = 0xD4; 
sbit RS0        = 0xD3; 
sbit OV         = 0xD2; 
sbit P          = 0xD0; 

/* PWR_CTL0 */
sbit VKEYEN     = 0xFC;
sbit PCHGEN     = 0xFB;

/* CLKCON0 */
sbit DSEN       = 0xB7;
sbit WDTWKEN    = 0xB6;
sbit SCLKSRC    = 0xB0;

/* RESETS0 */
sbit WDTCLR     = 0xA7;
sbit SSDF       = 0xA5;
sbit WDOF       = 0xA4;
sbit LVRF       = 0xA3;
sbit ABNF       = 0xA2;
sbit PINF       = 0xA1;
sbit PORF       = 0xA0;

/* P0 */
sbit P0_7       = 0x87;
sbit P0_6       = 0x86;
sbit P0_5       = 0x85;
sbit P0_4       = 0x84;
sbit P0_3       = 0x83;
sbit P0_2       = 0x82;
sbit P0_1       = 0x81;
sbit P0_0       = 0x80;

/* P1 */
sbit P06WKF     = 0x97;
sbit P04WKF     = 0x96;
sbit P03WKF     = 0x95;
sbit P1_4       = 0x94;
sbit P1_3       = 0x93;
sbit P1_2       = 0x92;
sbit P1_1       = 0x91;
sbit P1_0       = 0x90;

/* P2 & P3 */
sbit P2_7       = 0xDF;
sbit P2_6       = 0xDE;
sbit P2_5       = 0xDD;
sbit P2_4       = 0xDC;
sbit P2_3       = 0xDB;
sbit P3_0       = 0xD8;

/* INTCON0 */
sbit EA         = 0xAF; 
sbit ECHG       = 0xAE;
sbit ECMP       = 0xAD;
sbit ELV        = 0xAB;
sbit EOT        = 0xAA;
sbit EIIC       = 0xA9;
sbit EUART      = 0xA8;

/* INTCON1 */
sbit ET0        = 0xBE; 
sbit ET1        = 0xBD; 
sbit ET2        = 0xBC; 
sbit ET2C3      = 0xBB; 
sbit ET2C2      = 0xBA;
sbit ET2C1      = 0xB9;
sbit ET2C0      = 0xB8;

/* INTCON2 */
sbit ETICK      = 0xC5;
sbit EOC        = 0xC4;
sbit EOV        = 0xC3;
sbit EADC       = 0xC2;
sbit EX1        = 0xC1;
sbit EX0        = 0xC0;

/*  TCON  */
sbit TF1        = 0x8F; 
sbit TR1        = 0x8E;
sbit TPE1       = 0x8D;
sbit TBLNE1     = 0x8C;
sbit TF0        = 0x8B;
sbit TR0        = 0x8A;
sbit TPE0       = 0x89;
sbit TBLNE0     = 0x88; 

/*  T2CON  */
sbit TR2        = 0xCC;
sbit TCCS3      = 0xCB;
sbit TCCS2      = 0xCA;
sbit TCCS1      = 0xC9;
sbit TCCS0      = 0xC8; 

/* SCON */
sbit PAREN      = 0x9F;
sbit BRDSRC     = 0x9E;
sbit BR8        = 0x9D;
sbit REN        = 0x9C;
sbit RER        = 0x9B;
sbit BRPRE      = 0x9A;
sbit TI         = 0x99;
sbit RI         = 0x98;

/* ADCCHEN */
sbit AN7EN      = 0xEF;
sbit VOFFEN     = 0xEE;
sbit AN5EN      = 0xED;
sbit AN4EN      = 0xEC;
sbit AN3EN      = 0xEB;
sbit AN2EN      = 0xEA;
sbit IBATEN     = 0xE9;
sbit VBATEN     = 0xE8;

/* AFR */
#define P2OM0               (*(volatile unsigned char idata*)0xC9)
#define P2OM1               (*(volatile unsigned char idata*)0xCE)

#define IIC1CON             (*(volatile unsigned char idata*)0xD2)
#define IIC1STAT            (*(volatile unsigned char idata*)0xD3)
#define IIC1ADDR            (*(volatile unsigned char idata*)0xD4)
#define IIC1DAT             (*(volatile unsigned char idata*)0xD5)
#define IIC1DIV             (*(volatile unsigned char idata*)0xD6)

#define U1CON0              (*(volatile unsigned char idata*)0xD8)
#define U1CON1              (*(volatile unsigned char idata*)0xD9)
#define U1STAT              (*(volatile unsigned char idata*)0xDA)
#define U1BR                (*(volatile unsigned char idata*)0xDB)
#define U1TXDAT             (*(volatile unsigned char idata*)0xDC)
#define U1RXDAT             (*(volatile unsigned char idata*)0xDD)
#define U1FIFOCON           (*(volatile unsigned char idata*)0xDF)

#define SPICON0             (*(volatile unsigned char idata*)0xE0)
#define SPICON1             (*(volatile unsigned char idata*)0xE1)
#define SPISTAT             (*(volatile unsigned char idata*)0xE2)
#define SPIINTEN            (*(volatile unsigned char idata*)0xE3)
#define SPIINTSTAT          (*(volatile unsigned char idata*)0xE4)
#define SPICON2             (*(volatile unsigned char idata*)0xE5)
#define SPITXD              (*(volatile unsigned char idata*)0xE6)
#define SPIRXD              (*(volatile unsigned char idata*)0xE7)
#define SPIFCON             (*(volatile unsigned char idata*)0xE8)

#define P2PU1               (*(volatile unsigned char idata*)0xEC)

#define IOSLPWKF            (*(volatile unsigned char idata*)0xED)
#define IOSLPCON0           (*(volatile unsigned char idata*)0xEE)
#define IOSLPCON1           (*(volatile unsigned char idata*)0xEF)

#define SSPCON0             (*(volatile unsigned char idata*)0xF0)
#define SSPCON1             (*(volatile unsigned char idata*)0xF1)
#define SPPDAT              (*(volatile unsigned char idata*)0xF2)
#define SPPSTAT             (*(volatile unsigned char idata*)0xF3)
#define SPPTIM0             (*(volatile unsigned char idata*)0xF4)
#define SPPTIM4             (*(volatile unsigned char idata*)0xF4)
#define SPPTIM1             (*(volatile unsigned char idata*)0xF5)
#define SPPTIM5             (*(volatile unsigned char idata*)0xF5)
#define SPPTIM2             (*(volatile unsigned char idata*)0xF6)
#define SPPTIM3             (*(volatile unsigned char idata*)0xF7)

#define MLDCON              (*(volatile unsigned char idata*)0xF8)
#define MLDWKCON            (*(volatile unsigned char idata*)0xF9)
#define P2PU0               (*(volatile unsigned char idata*)0xFA)
#define P2OM2               (*(volatile unsigned char idata*)0xFE)
#define IOSTPCON1           (*(volatile unsigned char idata*)0xFF)

/* EFR */
#define UDBADR              (0x00)
#define UDBDAT              (0x01)
#define UDBCON              (0x02)

#define TSCHEN              (0x10)
#define TSCON               (0x11)
#define EXTMFP0             (0x12)
#define EXTMFP1             (0x13)
#define PEXTCON0            (0x14)
#define PEXTCON1            (0x15)

#define TSSTAT0             (0x1A)
#define TSSTAT1             (0x1B)
#define TSINT0              (0x1C)

#define TS01LV0             (0x20)
#define TS01LV1             (0x23)
#define TS01LV2             (0x26)
#define TSBVL               (0x2E)
#define TSBVH               (0x2F)

#define TS0VALL             (0x30)
#define TS0VALH             (0x31)
#define TS1VALL             (0x32)
#define TS1VALH             (0x33)

#define TS0OFFL             (0x40)
#define TS0OFFH             (0x41)
#define TS01FFL             (0x42)
#define TS01FFH             (0x43)

#define SPPCON              (0x50)
#define SPPVAL              (0x51)

#define LDOCON0             (0x60)
#define LDOCON1             (0x61)

#define RESETS1             (0x66)

#define OPACON              (0x6C)

#define EXTMFP6             (0x6D)

#define PEXTCON2            (0x70)
#define PEXTCON3            (0x71)

#define EXTMFP2             (0x74)
#define EXTMFP3             (0x75)
#define EXTMFP4             (0x76)
#define EXTMFP5             (0x77)

#endif